Limitations of VLSI Implementation of Delay-Insensitive Codes.

Venkatesh Akella Nitin H. Vaidya G. Robert Redinbo

Published in: FTCS (1996)

Keyphrases

vlsi implementation
delay insensitive
vlsi architecture
asynchronous circuits
low power
fir filters
high speed
error correction
filter bank
multiscale
feature space
low cost