Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays.

Davor Capalija Tarek S. Abdelrahman

Published in: FPL (2014)

Keyphrases

functional units
reconfigurable hardware
processing elements
hardware architecture
low cost
hardware implementation
peer to peer
finite state machines
field programmable gate array
high speed
social networks
hardware software
efficient implementation
parallel processors