Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era.
Aditya BansalSaibal MukhopadhyayKairshik RoyPublished in: CICC (2005)
Keyphrases
- low power
- power consumption
- single chip
- low power consumption
- low cost
- high speed
- vlsi architecture
- logic circuits
- digital signal processing
- cmos technology
- power reduction
- gate array
- wireless transmission
- power dissipation
- nm technology
- high power
- ultra low power
- power saving
- mixed signal
- circuit design
- design methodology
- real time
- vlsi circuits
- image sensor