A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications.
Dajiang ZhouJinjia ZhouJiayi ZhuPeilin LiuSatoshi GotoPublished in: ISSCC (2012)
Keyphrases
- video decoder
- free viewpoint
- memory subsystem
- low power consumption
- video codec
- view synthesis
- bitstream
- video coding standard
- real time
- multi view
- video coding
- inter view
- low cost
- macroblock
- low power
- virtual view synthesis
- high speed
- depth map
- stereoscopic video
- computer vision
- coding scheme
- embedded systems
- video compression
- power consumption
- d scene
- bit rate
- inter frame
- video quality
- motion estimation
- rate distortion
- depth information
- single chip
- application specific
- low bit rate
- motion compensation
- platform independent
- image processing
- compression algorithm
- motion compensated
- coding method
- virtual view
- computational complexity
- high quality
- multiple cameras