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VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor.
Shih-Chang Hsia
Bin-Da Liu
Jar-Ferr Yang
Bor-Long Bai
Published in:
IEEE Trans. Circuits Syst. Video Technol. (1995)
Keyphrases
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vlsi implementation
low power
high speed
power consumption
vlsi architecture
neural network
discrete cosine transform
low cost
massively parallel
pattern recognition
dct domain
single chip
fir filters