Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design.
Gwo Giun LeeMing-Jiun WangBo-Han ChenJiunFu ChenPing-Keng JaoChing-Jui HsiaoLing-Fei WeiPublished in: J. Signal Process. Syst. (2011)
Keyphrases
- learning algorithm
- dynamic programming
- improved algorithm
- times faster
- experimental evaluation
- preprocessing
- parallel implementation
- detection algorithm
- high accuracy
- reconfigurable architecture
- similarity measure
- np hard
- neural network
- recognition algorithm
- linear programming
- simulated annealing
- worst case
- cost function
- objective function
- data sets
- management system
- probabilistic model
- graph cuts
- theoretical analysis
- k means
- convergence rate
- pairwise
- computational complexity
- data flow
- systolic array
- pipelined architecture