5.10 A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs.
Junghyup LeePyoungwon ParkSeongHwan ChoMinkyu JePublished in: ISSCC (2015)
Keyphrases
- high speed
- worst case
- power consumption
- low power
- image quality
- flip flops
- cmos technology
- bit rate
- nm technology
- visual quality
- lower bound
- average case
- computational complexity
- error bounds
- upper bound
- peak signal to noise ratio
- feedback loop
- frame rate
- real time
- high frequency
- steady state
- focal plane
- image compression
- differential equations
- optical flow
- database
- reference frame
- np hard
- low voltage
- clock frequency
- image processing
- higher psnr
- low cost