Tensors masquerading as matchgates: Relaxing planarity restrictions on Pfaffian circuits.
Jacob W. TurnerPublished in: J. Comput. Syst. Sci. (2017)
Keyphrases
- high order
- high speed
- line drawings
- tensor voting
- tensor field
- lateral inhibition
- delay insensitive
- logic circuits
- circuit design
- analog circuits
- neural network
- analog vlsi
- vlsi circuits
- order tensor
- high level synthesis
- data sets
- computational framework
- higher order
- database
- asynchronous circuits
- knowledge base
- quantum computing