Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes.
Zhongfeng WangQingwei JiaPublished in: ISCAS (6) (2005)
Keyphrases
- low complexity
- low density parity check
- ldpc codes
- high speed
- vlsi architecture
- distributed video coding
- wyner ziv
- slepian wolf
- low power
- error correction
- decoding algorithm
- computational complexity
- message passing
- real time
- rate allocation
- turbo codes
- motion estimation
- channel coding
- multiple description coding
- image transmission
- frame rate
- source coding
- distributed source coding
- bit plane
- rate distortion
- video transmission
- video coding
- image compression
- video codec