A low-jitter and low-power phase-locked loop design.

Kuo-Hsing Chen Huan-Sen Liao Lin-Jiunn Tzou

Published in: ISCAS (2000)

Keyphrases

low power
low power consumption
single chip
low cost
logic circuits
power consumption
vlsi architecture
high speed
phase locked loop
gate array
cmos technology
digital signal processing
mixed signal
high power
power reduction
vlsi circuits
design process
real time