A low-power CMOS nine-channel 40-MHz binary detection system with self-calibrated 500-μV offset.
Carlos Azeredo LemeJose SilvaPaulo RodrigoJosé E. da FrancaPublished in: IEEE J. Solid State Circuits (1998)
Keyphrases
- low power
- high speed
- cmos technology
- power consumption
- low cost
- nm technology
- wireless transmission
- vlsi circuits
- high power
- single chip
- vlsi architecture
- digital signal processing
- real time
- ultra low power
- power reduction
- logic circuits
- low power consumption
- low voltage
- mixed signal
- delay insensitive
- multi channel
- ofdm system
- image sensor