TMA: Tera-MACs/W neural hardware inference accelerator with a multiplier-less massive parallel processor.
Hyunbin ParkDohyun KimShiho KimPublished in: Int. J. Circuit Theory Appl. (2021)
Keyphrases
- parallel processors
- compute intensive
- single processor
- processing elements
- hardware implementation
- neural network
- network architecture
- search problems
- precedence constraints
- parallel implementation
- field programmable gate array
- low cost
- hardware architecture
- floating point
- computing systems
- heuristic search
- computer architecture
- computer systems
- domain specific