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Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier.

Jae-Jin LeeGi-Yong Song
Published in: FPGA (2004)
Keyphrases
  • systolic array
  • hardware implementation
  • reconfigurable architecture
  • parallel architecture
  • fir filters
  • higher order
  • data flow