EJ-FAT Joint ESnet JLab FPGA Accelerated Transport Load Balancer.
Stacey SheldonYatish KumarMichael GoodrichGraham HeyesPublished in: CoRR (2023)
Keyphrases
- power reduction
- hardware implementation
- load balancing
- signal processing
- real time image processing
- high speed
- verilog hdl
- case study
- data mining
- hardware architectures
- field programmable gate array
- power consumption
- real time
- low power
- magnetic field
- power system
- hardware design
- software implementation
- website
- joint estimation
- image processing
- reconfigurable hardware
- computer vision