A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement.
Dong-Hyun YoonDong-Kyu JungKiho SeongTae-Hyeok EomJae-Soub HanJu Eon KimTony Tae-Hyoung KimKwang-Hyun BaekPublished in: A-SSCC (2021)
Keyphrases
- frequency band
- high speed
- band limited
- dual band
- power consumption
- noise level
- missing data
- random sampling
- dielectric constant
- low frequency
- flash memory
- sample size
- noise reduction
- signal to noise ratio
- hardware implementation
- floating point
- low pass
- noisy data
- sampled data
- row column
- high pass
- high frequency
- frequency domain