High-speed hardware architecture for high-definition videotex system.
Mitsuru MaruyamaHiroaki SakamotoYutaka IshibashiKazutoshi NishimuraPublished in: J. Electronic Imaging (1992)
Keyphrases
- high definition
- hardware architecture
- high speed
- real time
- hd video
- video communication
- video coding
- hardware implementation
- multimedia processing
- low power
- hardware architectures
- mpeg avc
- associative memory
- motion imagery
- processing elements
- high resolution
- frame rate
- field programmable gate array
- bit rate
- motion estimation
- pattern recognition