Highly Fault-Tolerant FPGA Processor by Degrading Strategy.
Yousuke NakamuraKei HirakiPublished in: PRDC (2002)
Keyphrases
- fault tolerant
- fault tolerance
- high speed
- distributed systems
- load balancing
- single chip
- gate array
- high availability
- safety critical
- parallel architecture
- fault isolation
- digital signal
- systolic array
- parallel processing
- state machine
- low cost
- field programmable gate array
- artificial intelligence
- hardware implementation