An Instruction Set Architecture Based Code Compression Scheme for Embedded Processors.
Sreejith K. MenonPriti ShankarPublished in: DCC (2005)
Keyphrases
- compression scheme
- instruction set architecture
- embedded processors
- image compression
- data compression
- instruction set
- single chip
- compression ratio
- compression algorithm
- parallel implementation
- source code
- hardware and software
- real time
- image segmentation
- index structure
- embedded systems
- high resolution
- lossless compression
- computer vision