A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation.
Jie GuoJun LiuBjörn MennengaGerhard P. FettweisPublished in: ASAP (2007)
Keyphrases
- back end
- level parallelism
- instruction set
- user friendly
- multi core processors
- publish subscribe
- building blocks
- industry standard
- data management
- detailed design
- parallel processing
- instruction scheduling
- data types
- parallel architecture
- version control
- floating point
- management system
- multithreading
- memory management
- data sets
- general purpose
- user interface