Self compensating low noise low power PLL design.
Vazgen MelikyanArmen DurgaryanArarat KhachatryanHayk ManukyanEduard MusaelyanPublished in: EWDTS (2013)
Keyphrases
- low power
- low power consumption
- single chip
- power consumption
- low cost
- high speed
- vlsi architecture
- gate array
- logic circuits
- design process
- power dissipation
- high power
- ultra low power
- digital signal processing
- power reduction
- mixed signal
- real time
- cmos technology
- wireless transmission
- vlsi circuits
- general purpose
- nm technology