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Low-Latency FPGA Design and Implementation of Hermitian Matrix Inversion Based on Partitioned Systolic Array for Massive MIMO.

Ke HanDaokun Li
Published in: ICTA (2022)
Keyphrases
  • systolic array
  • low latency
  • parallel architecture
  • hardware architecture
  • matrix inversion
  • high speed
  • real time
  • efficient implementation
  • hardware implementation
  • low cost
  • pairwise
  • dynamic programming
  • data processing