Low Power Design Analysis of PLL Components in Submicron Technology.
Kanika GargV. Sulochana VermaPublished in: ACITY (3) (2012)
Keyphrases
- low power
- gate array
- cmos technology
- single chip
- power consumption
- high speed
- low cost
- logic circuits
- mixed signal
- low power consumption
- vlsi circuits
- nm technology
- vlsi architecture
- wireless transmission
- power dissipation
- ultra low power
- digital signal processing
- real time
- high power
- low voltage
- design process
- multi channel