Low power and area efficient error tolerant design for parallel filters.
S. SandeepP. Sathish KumarPublished in: ICACCI (2018)
Keyphrases
- low power
- error tolerant
- single chip
- low cost
- high speed
- vlsi architecture
- power consumption
- low power consumption
- logic circuits
- gate array
- digital signal processing
- power reduction
- cmos technology
- parallel computing
- nm technology
- search algorithm
- design methodology
- shared memory
- pattern matching
- mixed signal
- graph matching