Power Optimization of 8-bit Register on Ultra Scale FPGA using Low Voltage CMOS I/O Standard.
Anupam YadavPublished in: ICCCNT (2021)
Keyphrases
- low voltage
- random access memory
- power management
- high speed
- power consumption
- design considerations
- power line
- cmos technology
- ibm power processor
- low cost
- reactive power
- real time
- low power
- power reduction
- image processing
- hardware implementation
- power dissipation
- field programmable gate array
- energy saving
- energy consumption
- signal processing
- object oriented