Low-power single-ended I/O circuit for binary interchip communications.
Franco FioriPublished in: ECCTD (2007)
Keyphrases
- low power
- high speed
- logic circuits
- power consumption
- low cost
- cmos technology
- vlsi circuits
- power reduction
- gate array
- delay insensitive
- power dissipation
- high power
- single chip
- input output
- digital signal processing
- mixed signal
- wireless transmission
- vlsi architecture
- low power consumption
- image processing
- nm technology