Reply to "Comments on the optimum CMOS tapered buffer problem".

Published in: IEEE J. Solid State Circuits (1994)

Keyphrases

finite element
email
power consumption
low cost
high speed
global optimum
power supply
circuit design
analog vlsi
low power
data sets
buffer allocation
delay insensitive
buffer size
focal plane
database
cellular automata
neural network
analog to digital converter