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An FPGA design for the Two-Band Fast Discrete Hartley Transform.

Lambros PyrgasParis KitsosAthanassios N. Skodras
Published in: ISSPIT (2016)
Keyphrases
  • hardware design
  • verilog hdl
  • hardware architecture
  • motion estimation
  • low cost
  • image reconstruction
  • field programmable gate array
  • single chip