Low power balun Design for 1.575 GHz in 90 nm CMOS rechnology.
Jacek GradzkiPublished in: DDECS (2012)
Keyphrases
- low power
- cmos technology
- power consumption
- high speed
- single chip
- nm technology
- low cost
- vlsi architecture
- logic circuits
- low power consumption
- power dissipation
- ultra low power
- digital signal processing
- power reduction
- mixed signal
- high power
- gate array
- image sensor
- analog to digital converter
- vlsi circuits
- cmos image sensor
- power saving
- delay insensitive
- wireless transmission
- real time
- signal processing