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Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms.

Muhsen OwaidaHantian ZhangCe ZhangGustavo Alonso
Published in: FPL (2017)
Keyphrases
  • hardware design
  • verilog hdl
  • low cost
  • real time
  • pairwise
  • high speed
  • hardware architecture
  • learning algorithm
  • training data
  • artificial neural networks
  • generalization ability
  • single chip