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A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering.
Qian Xie
Qian He
Xiao Peng
Ying Cui
Zhixiang Chen
Dajiang Zhou
Satoshi Goto
Published in:
SiPS (2011)
Keyphrases
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multi processor
decoding algorithm
ldpc codes
distributed processing
low density parity check
management system
processing elements
master slave
turbo codes
parallel computers
parallel processing
real time
massively parallel
shared memory
parallel architecture
coding scheme
computer simulation