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Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter.
Si-Seok Yang
Sung-Soo Min
Chan-Hyeok Eom
Rae-Young Kim
Gi-Young Lee
Published in:
IEEE Access (2022)
Keyphrases
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cost function
high accuracy
pairwise
classification accuracy
objective function
reduction method
transfer function
synthetic data
detection method
neural network
probabilistic model
experimental evaluation
dynamic programming
image analysis
classification method
high precision
preprocessing