Verification of a DSP IP cores by model checking.
H. N. NguyenP. KoumouBernard CandaeleMichel SarlotteChristian AntoineS. EmeriauPublished in: HLDVT (2002)
Keyphrases
- model checking
- temporal logic
- formal verification
- automated verification
- verification method
- model checker
- finite state machines
- finite state
- symbolic model checking
- partial order reduction
- temporal properties
- formal specification
- computation tree logic
- bounded model checking
- pspace complete
- asynchronous circuits
- concurrent systems
- formal methods
- reachability analysis
- transition systems
- process algebra
- artifact centric
- timed automata
- epistemic logic
- temporal epistemic