Reachability analysis in RTL circuits using k-induction bounded model checking.
Tonmoy RoyMichael HsiaoPublished in: HLDVT (2017)
Keyphrases
- reachability analysis
- bounded model checking
- model checking
- model based diagnosis
- temporal logic
- formal verification
- timed automata
- formal specification
- finite state
- high speed
- inductive learning
- linear temporal logic
- artificial intelligence
- concurrent systems
- epistemic logic
- transition systems
- modal logic
- machine learning
- hardware description language