Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture.
Dajiang LiuShouyi YinChongyong YinLeibo LiuShaojun WeiPublished in: IEICE Trans. Inf. Syst. (2012)
Keyphrases
- hardware implementation
- systolic array
- low cost
- optimization algorithm
- optimization problems
- network architecture
- affine transformation
- software architecture
- general purpose
- dynamic reconfiguration
- management system
- design methodology
- optimization methods
- optimization process
- field programmable gate array
- optimization model
- data flow
- reconfigurable hardware
- reconfigurable architecture
- data sets
- global optimization
- optimization method
- combinatorial optimization
- distributed systems
- architectural design
- discrete optimization
- hardware software
- image registration
- database systems
- information systems
- real time
- heterogeneous computing