Design of LVDS Transmitter with SLVDS mode for Low Power Applications in 55nm CMOS Technology.

Durga Prasanth Kumar Gavara G. Shekar

Published in: ICACCI (2018)

Keyphrases

cmos technology
low power
power consumption
low cost
high speed
single chip
power dissipation
low voltage
mixed signal
low power consumption
vlsi architecture
parallel processing
logic circuits
nm technology
digital signal processing
power reduction
silicon on insulator
gate array
design process