A 512-KB level-2 cache design in 45-nm for low power IA processor silverthorne.
Mohammed H. TaufiqueAlex OkpiszHaseeb N. AhmedJohn R. RileyMohammad M. HasanGianfranco GerosaPublished in: CICC (2008)
Keyphrases
- low power
- single chip
- high speed
- cmos technology
- gate array
- low cost
- power consumption
- low power consumption
- power reduction
- logic circuits
- nm technology
- vlsi architecture
- digital signal processing
- power dissipation
- cmos image sensor
- parallel processing
- memory hierarchy
- vlsi circuits
- power saving
- wireless transmission
- delay insensitive
- mixed signal
- low voltage
- knowledge base
- circuit design
- computer architecture
- wireless networks
- image processing