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Fast Block Motion Estimation With 8-Bit Partial Sums Using SIMD Architectures.
Chunjiang J. Duanmu
M. Omair Ahmad
M. N. S. Swamy
Published in:
IEEE Trans. Circuits Syst. Video Technol. (2007)
Keyphrases
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parallel architectures
single instruction multiple data
massively parallel
parallel algorithm
random variables
parallel processing
highly parallel
information retrieval
processor array
image processing
case study
operating system
parallel implementation
block cipher
array processor