Utilizing Symmetry when Model Checking under Fairness Assumptions: An Automata-theoretic Approach.
E. Allen EmersonA. Prasad SistlaPublished in: CAV (1995)
Keyphrases
- model checking
- finite state
- timed automata
- finite state machines
- temporal logic
- formal verification
- temporal properties
- formal specification
- model checker
- partial order reduction
- reachability analysis
- automated verification
- verification method
- symbolic model checking
- formal methods
- pspace complete
- transition systems
- resource allocation
- computation tree logic
- epistemic logic
- concurrent systems
- process algebra
- bounded model checking
- tree automata
- symmetry breaking
- finite automata
- regular expressions
- game theory
- asynchronous circuits