Timing diagram for CNPC interleaver implementation on FPGA.

Gwonhan Mun Kunseok Kang DeaHo Kim

Published in: ICAIIC (2021)

Keyphrases

hardware implementation
hardware architecture
real time image processing
case study
field programmable gate array
software implementation
hardware architectures
general purpose
high speed
error correction
implementation details
parallel architecture
fpga implementation
fpga device
hardware description language