High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures.

Rafael A. Arce-Nazario Manuel Jiménez Domingo Rodríguez

Published in: FPL (2006)

Keyphrases

high level
signal processing
low level
digital signal
discrete fourier transform
real time
higher level
hardware design
frequency domain
low cost
gabor transform
non stationary
high speed
programming language
hardware implementation
single chip
discrete space
hardware architecture
original signal
arbitrary size