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A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device.

Yong-Hyun KimJong-Moon ChoiJe-Joong WooEun-Je ParkSang-Won KimKee-Won Kwon
Published in: ICEIC (2019)
Keyphrases
  • floating gate
  • sparse matrix
  • circuit design
  • floating point
  • weight vector
  • rows and columns
  • hardware implementation
  • real time
  • feature vectors
  • low cost
  • high speed