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A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS.
Bob Verbruggen
Masao Iriguchi
Jan Craninckx
Published in:
ISSCC (2012)
Keyphrases
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power consumption
power supply
analog to digital converter
circuit design
hd video
high speed
dynamic environments
parameter estimation
image reconstruction
sar images
synthetic aperture radar
data flow
metal oxide semiconductor