A low-power ASIC implementation of 2Mbps antenna-rake combiner for WCDMA with MRC and LMS capabilities.
Alireza TarighatEugene GrayverAhmed M. EltawilJean-François FrigonGennady Y. PoberezhskiyHanli ZouBabak DaneshradPublished in: CICC (2005)
Keyphrases
- low power
- vlsi architecture
- single chip
- power consumption
- low cost
- high speed
- cmos technology
- signal processor
- vlsi circuits
- circuit design
- ultra low power
- hardware implementation
- design methodology
- digital signal processing
- low power consumption
- vlsi implementation
- hardware architecture
- high power
- wireless transmission
- low complexity
- high definition television
- power dissipation
- mixed signal
- computer simulation
- image sensor
- power reduction
- efficient implementation