FATE: fast and accurate timing error prediction framework for low power DNN accelerator design.
Jeff Jun ZhangSiddharth GargPublished in: ICCAD (2018)
Keyphrases
- low power
- power consumption
- single chip
- vlsi architecture
- low cost
- high speed
- low power consumption
- logic circuits
- cmos technology
- digital signal processing
- gate array
- design process
- prediction error
- power dissipation
- design considerations
- high power
- real time
- design methodology
- power reduction
- mixed signal
- vlsi circuits
- image processing