A unified and pipelined hardware architecture for implementing intra prediction in HEVC.
Yuebing JiangDaniel LlamoccaMarios S. PattichisGangadharan EsakkiPublished in: SSIAI (2014)
Keyphrases
- intra prediction
- hardware architecture
- avc video coding
- video compression
- coding efficiency
- hardware implementation
- pixel wise
- spatial correlation
- mode decision
- video coding standard
- video transmission
- image coding
- field programmable gate array
- macroblock
- intra coding
- efficient implementation
- motion estimation
- motion compensation
- motion compensated
- video coding
- bit rate
- high quality
- image segmentation
- machine learning
- associative memory
- rate distortion
- motion vectors