A high throughput hardware architecture for deblocking filter in HEVC.
P. KopperundeviMatcha Surya PrakashShaik Rafi AhamedPublished in: Signal Process. Image Commun. (2022)
Keyphrases
- high throughput
- hardware architecture
- deblocking filter
- video coding standard
- low bit rate
- video codec
- video compression
- motion compensation
- coding method
- video coding
- blocking artifacts
- low power
- hardware implementation
- coding efficiency
- discrete cosine transform
- microarray
- macroblock
- motion compensated
- motion vectors
- digital video
- motion estimation
- spatial domain
- bit rate
- field programmable gate array
- image compression
- video streaming
- rate distortion
- image quality
- inter frame
- data acquisition
- high speed
- post processing
- intra prediction
- visual quality
- neural network
- data analysis
- block size
- image coding
- associative memory
- high frequency
- video data
- signal processing
- coding scheme