A 40-170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS.

Kunhee Cho Ranjit Gharpurey

Published in: IEEE J. Solid State Circuits (2016)

Keyphrases

high speed
cmos technology
nm technology
low power
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power consumption
parallel processing
random access memory
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vlsi circuits