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A DMR logic for mitigating the SET induced soft errors in combinational circuits.
Jiajin Zhang
Yang Housen
Yankang Du
Gao Quan
Peng Lin
Zhang Yue
Lichang Chen
Published in:
IEICE Electron. Express (2016)
Keyphrases
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partially ordered
data sets
small number
partial order
logic circuits
delay insensitive
databases
neural network
learning algorithm
decision trees
expert systems
user defined
modal logic
logic synthesis