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A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture.

Patrick Y. WuVincent Sin-Luen CheungHoward C. Luong
Published in: IEEE J. Solid State Circuits (2007)
Keyphrases
  • analog to digital converter
  • data flow
  • image sensor
  • low cost
  • random access memory
  • real time
  • management system
  • low power
  • cmos image sensor
  • high speed
  • parallel architecture
  • image processing
  • single chip
  • analog vlsi