A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL.

Yanfeng Li Ni Xu Woogeun Rhee Zhihua Wang

Published in: ISCAS (2014)

Keyphrases

phase locked loop
user friendly
high speed
data conversion
high voltage
neural network
image processing
multimedia
multiresolution
control system
response time
circuit design