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A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL.

Yanfeng LiNi XuWoogeun RheeZhihua Wang
Published in: ISCAS (2014)
Keyphrases
  • phase locked loop
  • user friendly
  • high speed
  • data conversion
  • high voltage
  • neural network
  • image processing
  • multimedia
  • multiresolution
  • control system
  • response time
  • circuit design